The present invention is directed to electrical data pathway structures for very high-speed digital data transfer. High-speed integrated circuits such as gallium arsenide digital memory chips, microprocessors and logic components and superconductive Josephson junction devices have access or processing cycle times of about one nanosecond or less. However, a significant limitation on the performance of data processing systems utilizing such high speed devices is the speed of the data pathway system which interconnects the components of the system. Conventional data pathway backplane systems such as typical motherboard-daughterboard data pathway circuit board interconnection systems do not function at speeds adequate to realize the full potential of high speed integrated circuits. Very high speed backplane data pathway systems operating at speeds up to and greater than 500 megahertz would be desirable for more fully realizing the potential processing speed of such systems. Moreover, fast gallium arsenide or other very high speed digital data processing devices are typically synchronized with a master clock, requiring transmission of a clock signal to each circuit component or subsystem which is required to operate synchronously with the other components. However, while high speed signal transmission may be readily accomplished from one transmitter to one or two single receivers, the provision of data bus taps for multiple receivers distributed along a signal line creates complex, cumulatively interactive impedance variations which impede digital signal transmission at high speeds. Typically at high signal rates, interference from multiple taps (which generally increases with the number of taps) is so pronounced that component system fan out is significantly limited (e.g., to two clock ports), thus requiring excessive buffering for interconnection of multiple components, increased component count and resulting cycle delays. Accordingly, in order to fully utilize the high processing speed capabilities of integrated circuits such as those made from high electron mobility III-V materials, there is a need for passive and active high speed integrated circuit interconnection systems which are capable of transmitting and/or receiving digital data electrically at high speed from single or multiple sources to one or more of multiple target receivers. In this regard, passive high-speed data transmission systems including various array processing architectures, redundant processing architectures and systems utilizing logic fanout to multiple receiver barrels would be desirable which can function at speeds up to 500 MHz or more. There is also a need for active, high speed integrated circuit interconnection systems capable of both transmitting and receiving information from multiple sources and targets at very high data transmission rates, such as 500 MHz to 2 Gigahertz or more. Such systems would facilitate highly concurrent (pipelined) data processing structures, allow "handshake" capability for enhanced system designs, facilitate high performance systems utilizing multiple processor boards in complex systems, and provide multiple memory board designs without creating excessively large bus structures.
Accordingly, it is an object of the present invention to provide very high-speed (e.g., 500 megabit per second to 2 or more gigabits per second data transmission rate per channel) data transmission pathways for multiple receivers which permit effective utilization of very fast integrated circuit components. It is a further object to provide both passive and active high speed data transmission systems for transmitting to multiple receivers along the data pathway. It is a further object to provide integrated circuit components which are particularly suited for use in high speed data pathway systems. These and other objects of the invention will be apparent from the following description and the accompanying drawings.